1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of reducing power consumption in semiconductor devices, such as FINFET devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure.
FinFET designs use “fins” that may be formed on the surface of a semiconductor wafer using selective-etching processes. The fins may be used to form a raised channel between the gate and the source and drain of a transistor. The gate is then deposited such that it wraps around the fin to form a trigate structure. Since the channel is extremely thin, the gate would generally have a greater control over the carriers within. However, when the transistor is switched on, the shape of the channel may limit the current flow. Therefore, multiple fins may be used in parallel to provide greater current flow for increased drive strength.
FIG. 1 illustrates a stylized cross-sectional depiction of a state-of-the-art FinFET device. A FinFET device 100 illustrated in FIG. 1 comprises a plurality of “fins” 110. The semiconductor device may be position to a vertical orientation, creating one or more fins 110. The source and drain of the FinFET are placed horizontally along the fin. A high-k metal gate 120 wraps over the fin, covering it on three sides. The gate 120 defines the length of the FinFET device. The current flow occurs along an orthogonal crystal plane in a direction parallel to the plane of the semiconductor wafer. The electrically significant height of the fin (labeled H) is typically determined by the amount of oxide recess in the fin reveal step and hence is constant for all fins 110.
The thickness of the fin (labeled Tfi) determines the short channel behavior of the transistor device and is usually small in comparison with the height H of the fin 110. The pitch (labeled P) of the fins is determined by lithographic constraints and dictates the wafer area to implement the desired device width. A small value of the pitch P and a large value of the height H enable a better packing of the devices per square area resulting in a denser design, or more efficient use of silicon wafer area.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the depletion width under the channel and thereby reduce so-called short channel effects. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. However, FinFET devices still exhibit some performance-limiting characteristics. One such characteristic that is detrimental to all forms of semiconductor devices, both FinFETs and planar FETs, is off-state leakage currents. Ideally, off-state leakage current is minimized to increase device performance.
FinFET technology has emerged as a solution to reduce problems associated with leakage currents, gate leakage, excessive power consumption, etc. Compared to conventional MOSFET technology, FinFET technology can offer superior short channel effects. For example, FinFET technology may allow for more efficient flow of carriers through the channel underneath the gate electrode, therefore, efficiently turning off the FinFET transistor.
One problem associated with the FinFET device is that the freedom to select the drive strength is reduced. The drive strength can only be improved during layout by adding more fins. Therefore, the effective width of the FinFET device may become quantized. Generally, at least two fins are formed in FinFET devices, sometimes more. Due to the dense nature of modern semiconductor devices, a large number of fins may be present. The fins may cause high active power-consumption.
In a FINFET, the device-width quantum is determined by the height H of the fin, with each fin providing 2H of device width. With such quantization in device width, it becomes more difficult to achieve desired beta ratios using FinFETs, which places a constraint on the power-performance tradeoffs associated with the designs.
State-of-the-art solutions include fine-tuning various blocks formed on a semiconductor device, such as a FINFET device for lower power. However, these state-of-the-art solutions may require redesigning the layout of the semiconductor device after an analysis of the performance-power tradeoff parameters is performed. The redesign cycle would generally cause delays and expense during the manufacturing and testing processes. For example, an estimate of the amount of current flow (saturation drain current) may be made during the design stage of a semiconductor device. Based upon this estimate, a number of fins may be designed into the FinFET device. However, after the product design, a better understanding of the floor plan and the routing of the device is obtained, which leads to a better estimate of the amount of current flow. Upon this new, more accurate estimate, it may be apparent that the number of fins that were used in the design may be excessive in some portions of the semiconductor device, thereby causing needless power consumption in the semiconductor device. However, changing the design or the product to correct this problem at this stage may be time consuming and costly.
The present disclosure may address and/or at least reduce one or more of the problems identified above.